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| White Electronic Designs W3EG7265S-JD3 PRELIMINARY* 512MB - 2x32Mx72 DDR SDRAM REGISTERED, w/PLL FEATURES Double-data-rate architecture DDR200 and DDR266 * JEDEC design specificaitons Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2,5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power Supply: 2.5V 0.2V JEDEC standard 184 pin DIMM package * PCB height: 30.48mm (1.20") NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change without notice. DESCRIPTION The W3EG7265S is a 2x32Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of eighteen 32Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 184 Pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. OPERATING FREQUENCIES DDR266 @CL=2 Clock Speed CL-tRCD-tRP 133MHz 2-2-2 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 January 2005 Rev. 3 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs PIN CONFIGURATIONS Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 Symbol VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VCC *CK1 *CK1# VSS DQ10 DQ11 CKE0 VCC DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCC DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 CB0 CB1 VCC Pin 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 Symbol DQS8 A0 CB2 VSS CB3 BA1 DQ32 VCC DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCC WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC *CK2# DQ48 DQ49 VSS *CK2# *CK2 VCC DQS6 DQ50 DQ51 VSS VCCIQ DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL Pin 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 Symbol VSS DQ4 DQ5 VCC DQM0 DQ6 DQ7 VSS NC NC *A13 VCC DQ12 DQ13 DQM1 VCC DQ14 DQ15 CKE1 VCC *BA2 DQ20 A12 VSS DQ21 A11 DQM2 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCC DQM3 A3 DQ30 VSS DQ31 CB4 CB5 VCC CK0 CK0# Pin 139 140 141 VCC 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Symbol VSS DQM8 A10 CB6 VCC CB7 VSS DQ36 DQ37 VCC DQM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCC CS0# CS1# DQM5 VSS DQ46 DQ47 CS3# VCC DQ52 DQ53 NC VCC DQM6 DQ54 DQ55 VCC NC DQ60 DQ61 VSS DQM7 DQ62 DQ63 VCC SA0 SA1 SA2 VCC SPD * Not Used W3EG7265S-JD3 PRELIMINARY PIN NAMES A0 - A12 BA0-BA1 DQ0-DQ63 CB0-CB7 DQS0-DQS8 CK0 CK0# CKE0, CKE1 CS0#, CS1# RAS# CAS# WE# DQM0-DQM8 VCC VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC RESET# VCCID Address input (Multiplexed) Bank Select Address Data Input/Output Check bits Data Strobe Input/Output Clock Input Clock Input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Identification Flag No Connect Reset Enable VCC Identification Flag January 2005 Rev. 3 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs FUNCTIONAL BLOCK DIAGRAM RCS1# RCS0# DQS0 DQM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS 120 CK0 CK0# PLL W3EG7265S-JD3 PRELIMINARY DQS4 DQM4 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQM5 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQM6 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQM7 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS# DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS# DQS DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM REGISTER X 2 CS0# CS1# BA0, BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE# PCK PCK# R E G I S T E R S SERIAL PD RCS0# RCS1# RBA0-RBA1 RA0-RA12 RRAS# RCAS# RCKE0 RCKE1 RWE# RESET# BA0-BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE: DDR SDRAMs CKE: DDR SDRAMs WE#: DDR SDRAMs VCCSPD VCCQ VCC VREF VSS SPD SCL WP SDA A0 A1 A2 SA0 SA1 SA2 DDR SDRAMS DDR SDRAMS DDR SDRAMS DDR SDRAMS NOTE: All resistor values are 22 ohms unless otherwise specified. January 2005 Rev. 3 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCC TSTG PD I0S Value -0.5 - 3.6 -1.0 - 3.6 -55 - +150 18 50 W3EG7265S-JD3 PRELIMINARY Units V V C W mA Note: Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability DC CHARACTERISTICS 0C TA 70C, VCC = 2.5V 0.2V Parameter Supply Voltage Supply Voltage Reference Voltage Termination Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Symbol VCC VCC VREF VTT VIH VIL VOH VOL Min 2.3 2.3 1.15 1.15 VREF + 0.15 -0.3 VTT + 0.76 -- Max 2.7 2.7 1.35 1.35 VCC + 0.3 VREF - 0.15 -- VTT - 0.76 Unit V V V V V V V V CAPACITANCE TA = 25C, f = 1MHz, VCC = 2.5V 0.2V Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CK0,CK0#) Input Capacitance (CS0#) Input Capacitance (DQM0-DQM8) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63)(DQS) Data input/output capacitance (CB0-CB7) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT Max 6.5 6.5 6.5 5.5 6.5 13 6.5 13 13 Unit pF pF pF pF pF pF pF pF pF January 2005 Rev. 3 4 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs IDD SPECIFICATIONS AND TEST CONDITIONS 0C TA 70C, VCC = 2.5V 0.2V, VCC = 2.5V 0.2V Includes DDR SDRAM component only DDR266@CL=2.0 Max 2025 W3EG7265S-JD3 PRELIMINARY Parameter Operating Current Symbol IDD0 Conditions One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-Down mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR266@CL=2.5 Max 1980 DDR200@CL=2 Max 1980 Units mA Operating Current IDD1 2340 2295 2295 mA Precharge PowerDown Standby Current Idle Standby Current IDD2P 72 72 72 rnA IDD2F 810 810 810 mA Active Power-Down Standby Current Active Standby Current IDD3P IDD3N 450 900 450 900 450 900 mA mA Operating Current IDD4R 2250 2250 2250 mA Operating Current IDD4W 2115 2115 2115 rnA Auto Refresh Current Self Refresh Current Operating Current IDD5 IDD6 IDD7A 3015 72 4050 3015 72 4050 3015 72 4050 mA mA mA January 2005 Rev. 3 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs IDD SPECIFICATIONS AND TEST CONDITIONS 0C TA 70C, VCC = 2.5V 0.2V, VCC = 2.5V 0.2V Includes PLL and register power DDR266@CL=2.0 Max 2610 W3EG7265S-JD3 PRELIMINARY Parameter Operating Current Symbol IDD0 Conditions One device bank; Active - Precharge; tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN); tCK=tCK (MIN); lOUT = 0mA; Address and control inputs changing once per clock cycle. All device banks idle; Power-down mode; tCK=tCK (MIN); CKE=(low) CS# = High; All device banks idle; tCK=tCK (MIN); CKE = high; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM. One device bank active; Power-Down mode; tCK (MIN); CKE=(low) CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS (MAX); tCK=tCK (MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. Burst = 2; Reads; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; TCK= TCK (MIN); lOUT = 0mA. Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN); DQ,DM and DQS inputs changing once per clock cycle. tRC = tRC (MIN) CKE 0.2V Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK (MIN); Address and control inputs change only during Active Read or Write commands. DDR266@CL=2.5 Max 2565 DDR200@CL=2 Max 2565 Units mA Operating Current IDD1 2925 2880 2880 mA Precharge PowerDown Standby Current Idle Standby Current IDD2P 72 72 72 rnA IDD2F 1120 1120 1120 mA Active Power-Down Standby Current Active Standby Current IDD3P IDD3N 450 1210 450 1210 450 1210 mA mA Operating Current IDD4R 2835 2835 2835 mA Operating Current IDD4W 2700 2700 2700 rnA Auto Refresh Current Self Refresh Current Operating Current IDD5 IDD6 IDD7A 3635 347 4635 3635 347 4635 3635 347 4635 mA mA mA January 2005 Rev. 3 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT: ONE BANK 1. Typical Case: VCC = 2.5V, T = 25C 2. Worst Case: VCC = 2.7V, T = 10C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lOUT = 0mA 4. Timing patterns * DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRCD = 2*tCK, tRAg = 5*tCK Read: A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst * DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst * DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst W3EG7265S-JD3 PRELIMINARY IDD7A: OPERATING CURRENT: FOUR BANKS 1. Typical Case: VCC = 2.5V, T = 25C 2. Worst Case: VCC = 2.7V, T = 10C 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 4. Timing patterns * DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst * DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL = 2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst * DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2, BL = 4, tRRD = 2*tCK, tRCD = 3*tCK Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst Legend: A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 January 2005 Rev. 3 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC Characteristics Parameter Access window of DQs from CK, CK# CK high-level width CK low-level width Clock cycle time CL=2.5 CL=2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK, CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK, CK# Data-out low-impedance window from CK, CK# Address and control input hold time (fast slew rate) Address and control input set-up time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period Symbol tAC tCH tCL tCK (2.5) tCK (2) tDH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIHf tISf tIHs tISs tIPW tMRD tQH tQHS tRAS tRAP tRC tRFC 40 15 60 75 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 40 20 65 75 0.75 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP-tQHS 0.75 120,000 Min -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 0.75 0.2 0.2 tCH, tCL +0.75 +0.75 262 Max +0.75 0.55 0.55 13 13 Min -0.75 0.45 0.45 7.5 10 0.5 0.5 1.75 -0.75 0.35 0.35 0.5 1.25 +0.75 265/202 Max +0.75 0.55 0.55 13 13 Units ns tCK tCK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 21 15 13,14 18 8,19 8,20 6 6 6 6 13,14 16 16 22 22 14,17 14,17 17 Notes January 2005 Rev. 3 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs W3EG7265S-JD3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VCC Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command Symbol tRCD tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR NA tREFC tREFI tVTD tXSNR tXSRD 0 75 200 Min 15 15 0.9 0.4 15 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0 75 200 0.6 1.1 0.6 262 Max Min 20 20 0.9 0.4 15 0.25 0 0.4 15 1 tQH-tDQSQ 70.3 7.8 0.6 1.1 0.6 265/202 Max Units ns ns tCK tCK ns tCK ns tCK ns tCK ns s s ns ns tCK 13 12 12 10,11 9 19 Notes January 2005 Rev. 3 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Notes 1. 2. All voltages referenced to VSS Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at normal reference / supply voltage levels, but the related specifications and device operations are guaranteed for the full voltage range specified. Outputs are measured with equivalent load: 12. 11. W3EG7265S-JD3 PRELIMINARY It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be high during this time, depending on tDQSS. The refresh period is 64ms. This equates to an average refresh rate of 15.625s or 7.8125s. However, an AUTO REFRESH command must be asserted at least once every 140.6s or 70.3s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications - tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycled variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. Referenced to each output group: x8 = DQS with DQ0-DQ7. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. JEDEC specifies CK and CK# input slew rate must be > 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rates exceeds 4V/ns, functionality is uncertain. tHP min is the lesser of tCL min and tCH min actually applied to the device CK and CK# inputs, collectively during bank active. This maximum value is derived from the referenced test load. In practice, the values obtained in a typical terminated design may reflect up to 310ps less for tHZ (MAX) and last DVW. tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX) condition. For slew rates greater than 1V/ns the (LZ) transition will start about 310ps earlier. CKE must be active (High) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). 3. VTT TT 50 Reference Point 30pF 13. Output (VOUT (VOUT) 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are defined in the SSTL_ 2 standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [high] level). Command/Address input slew rate = 0.5V/ns. For -75 with slew rates 1V/ns and faster, tIS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.3 x VCC is recognized as LOW. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) and begins driving (LZ). The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 14. 15. 5. 16. 17. 6. 18. 19. 7. 8. 20. 21. 9. 10. 22. January 2005 Rev. 3 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs ORDERING INFORMATION FOR JD3 Part Number W3EG7265S262JD3 W3EG7265S265JD3 W3EG7265S202JD3 Speed 133MHz/266Mb/s 133MHz/266Mb/s 100MHz/200Mb/s CAS Latency 2 2.5 2 tRCD 2 3 2 W3EG7265S-JD3 PRELIMINARY tRP 2 3 2 Height* 30.48 (1.20") 30.48 (1.20") 30.48 (1.20") NOTE: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR JD3 133.48 (5.255" MAX.) 131.34 (5.171") 128.95 (5.077") 3.99 (0.157 (2x)) 3.99 (0.157) (MIN) 4.06 (0.160 MAX) 17.78 (0.700) 10.01 (0.394) 6.35 (0.250) 64.77 (2.550) 1.27 (0.050 TYP.) 30.48 (1.20 MAX) 6.35 (0.250) 1.78 (0.070) 49.53 (1.950) 2.31 (0.091) (2x) 3.00 (0.118) (4x) 1.27 0.10 (0.050 0.004) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES). January 2005 Rev. 3 11 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 512MB - 2x32Mx72 DDR SDRAM REGISTERED, w/PLL W3EG7265S-JD3 PRELIMINARY Revision History Rev # Rev 0 Rev 1 History Created Datasheet 1.1 Updated CAP & IDD Specs. 1.2 Changed package option to JEDEC "JD3" 1.3 Moved from Advanced to Preliminary Release Date 5-22-02 6-04 Status Advanced Preliminary Rev 2 Rev 3 2.1 Added AC Specs 3.1 Added lead-free and RoHS notes 3.2 Provided source control availability 3.3 Added industrial temperature options 11-04 1-05 Preliminary Preliminary January 2005 Rev. 3 12 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
Price & Availability of W3EG7265S202JD3
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